The present invention relates to the field of semiconductor memories, particularly to non-volatile memories, and even more particularly to memories in which operations to modify the content thereof, either by writing or by erasure, are performed electrically. In particular, the present invention relates to flash memories.
Flash memories are being used and will be used to an ever greater extent in various applications. This is due to a large degree to the fact that these memories can be written and erased electrically, to the availability of technological processes which enable high-capacity flash memories to be produced, and to the low cost of these memories.
Some of these applications involve the ability to modify data at the level of octets (bytes, eight bits), of words (sixteen bits) or of extended words (long words, thirty-two or sixty-four bits).
In current flash memories, particularly in flash memories with so-called NOR architecture, which are the most widespread at the moment, the matrix (array) of memory cells or memory matrix is normally divided into a certain number of sectors each of which contains a particular number of physical rows (word lines) or of physical columns (bit lines). The dimensions of the sectors may vary considerably; however, the smallest sector dimension which can be achieved in practice at reasonable cost by the conventional technique for dividing the matrix amounts to a few kbytes. A typical division of the memory matrix of a flash memory provides, for example, identical sectors each of 64 kbytes which are intended, in use, to store substantially invariable portions of micro-code, with a few smaller sectors, for example of from 2 to 4 kbytes, which can advantageously be used for storing parameters which are to vary with some frequency.
In a typical flash-memory architecture, all of the memory cells which make up a given sector are formed in a respective semiconductor well with p-type conductivity which in turn is formed in a respective semiconductor well with n-type conductivity. A typical method of performing the operation to xe2x80x9cerasexe2x80x9d the memory cells of a sector provides for the selection of all of the rows of the sector which are to be erased; the electric field necessary to erase the memory cells of the sector is supplied partly by biasing the rows to a negative potential and partly by biasing the semiconductor well with p-type conductivity (the bulk of the memory cells) to a positive potential. All of the memory cells of the sector are thus erased simultaneously. The sectors therefore represent the units of memory which can be erased independently of the others.
The main obstacle to the reduction of the size of the sectors in flash memories is the considerable increase in area (xe2x80x9coverheadxe2x80x9d) in terms of the ratio between the total area and the area occupied by the memory cells of the sector. This increase in area can be quantified as about 10% for 0.5 Mbit sectors and rises to 100% for sectors with dimensions of a few kbits.
To achieve better resolution without introducing the above-mentioned considerable increase in area, it is possible to modify the architecture of the circuits for selecting the rows, rendering them capable of selecting only one row during the erasure operation instead of all of the rows. The positive potential is thus still applied to the semiconductor well with p conductivity but the negative potential necessary for the erasure is applied solely to the row selected and only the memory cells belonging to the row selected are therefore erased. With reference to the example given above, this technique enables the dimensions of a memory block, that is, of the unit which can be erased individually, to be reduced to values of the order of magnitude of one kbit, with a very small increase in area since the modifications which have to be made to the circuits for decoding and selecting the rows in order to render them capable of transferring a negative voltage solely to the row selected for erasure, instead of to all of the rows of the block, do not significantly affect the area occupied.
However, this technique has two main disadvantages. In the first place, the resolution which can thus be achieved is nevertheless still insufficient for some applications; an ability to erase individually memory blocks with dimensions of a few kbits may not be sufficient for some applications which, as mentioned, would involve the ability to modify data at byte, word, or long-word level.
A second disadvantage of the technique described lies in the fact that, during erasure, since the semiconductor well with p conductivity in which all of the cells of the sector are formed is nevertheless biased to the positive potential, the cells which are not selected are also subjected to a stress which, in the long term, may lead to destruction of the data stored therein.
According to the present invention, a semiconductor memory, particularly of the electrically programmable and erasable type, comprising at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns of memory cells, characterized in that the columns of memory cells of the at least one two-dimensional array are grouped in a plurality of packets of columns, and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed, the semiconductor regions with the first type of conductivity being formed in a common semiconductor region with a second type of conductivity, opposite to the first type.